Given today's high clock rates and transmission line effects when signals must travel between integrated circuit chips, changes along signal paths can occur over time that affect signal timing. As a system heats and cools during operation, and/or develops hot and cool spots, the skew between data bits, or between data bits and strobe signals can likewise change as data bit signals and strobe signals travel off chip and between chips through various system-level paths. Therefore, it would be useful to have a way to perform dynamic timing calibration and re-calibration from time to time during system operation, and to do so quickly and dynamically without affecting the normal operation of the system.
One application where such a continuously adaptive calibration or training mechanism for data interface timing calibration is especially useful is to compensate for variable system-level delays in dynamic memory interfaces where DQ data bits can develop a skew problem with respect to the DQS strobe used to sample them, or where the optimal DQS strobe timing over all data bits varies during the functional operation of the system. Similarly, at the timing interface between the Phy and internal core clock domains in a dynamic memory based controller system, the timing relationship between an internal capture clock and data coming from the Phy can also drift due to system-level delays. In addition, jitter can develop between data bits and strobes, or between signals in different clock domains, and it would also be useful to resolve jitter issues while performing a continuous timing calibration function.
The solution previously described herein and now published in issued U.S. patents also assigned to applicant is shown in U.S. Pat. Nos. 8,947,140, 8,941,422, 8,941,423, 9,100,027 also known herein as CAT (Continuous Adaptive Training) This functionality is able to continuously monitor the performance of a data interface circuit by creating a parallel data path—a reference path—that mimics the function of the actual data path in use—the mission path. Thus constantly determining revised timing parameters as necessary that can be constantly updated to the mission path.
An approach for de-skew of data bits in a data interface is described in U.S. application Ser. No. 14/273,416 assigned to Applicant for bit-levelling calibration known herein as ABC. With ABC, a known data pattern is read by the data interface being calibrated. This function is typically utilized at power-on reset time, however is also designed so that it runs relatively quickly and while it does disturb normal system operation, it can be performed during the operation of, for instance, a DDR memory interface with relatively small periods of interruption. To perform such a calibration, the previously disclosed ABC solution requires the DDR system to be temporarily placed in a non-active condition in order to be run, including where necessary replacing application data in the DDR memory with a known calibration data pattern. The disadvantage to this is there will be an impact on system bandwidth whenever an ABC update/re-calibration must be done. Additionally it is incumbent upon the system to determine when the ABC update should be run.
Therefore, it would useful to have a dynamic capability to adjust the timing for a data interface to compensate for drift over time, such that adjustments are performed without any effect on the continuous operation of the system. Such a new capability could be added-on to any initial calibration method that operates at system power-on time, and assuming that optimal timing points were obtained by the initial calibration method for all data bits of interest, the new capability would continually make adjustments when necessary to compensate for drift over time, and do so without disturbing normal system operation. Note that in addition to performing an initial calibration at power-on time, there are two other circumstances where such an initial calibration is useful:                1) Where a dynamic frequency or voltage scaling event has occurred. For example if in order to save power the system operational frequency is reduced or the power supply voltage is reduced, it may be appropriate to re-run an initial calibration similar to that run at power-on.        2) If the DRAM has been in a self-refresh mode for an extended period, then upon leaving that mode is it may be appropriate to re-run the initial calibration similar to that run at power-on.        